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XC25BS8 Series
GENERAL DESCRIPTION
ETR1506-003
Ultra Small PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits Preliminary
The XC25BS8 series is an ultra small PLL clock generator IC which can generate a high multiplier output up to 4095 from an input frequency as low as 8kHz. The series includes a divider circuit, phase/frequency comparator, charge pump, and VCO so it is possible to configure a fully operational circuit with a few external components like one low-pass filter capacitor. The Input divider ratio (M) can be selected from a range of 1 to 2047, the output divider ratio (N) can be selected from a range of 1 to 4095 and they are set internally by using laser timing technologies. Output frequency (fQ0) is equal to input clock frequency (fCLKin) multiplied by N/M. Output frequency range is 1MHz to 100MHz. Reference clock from 8kHz to 36MHz can be input as the input clock. The IC stops operation and current drain is suppressed when a low level signal is input to the CE pin which greatly reduces current consumption and produces a high impedance output. The setting of the input divider ratio (M), output divider ratio (N), and charge pump current (Ip) are factory fixed semi-custom. Please advise your Torex sales representative of your particular input/output frequency and supply voltage specifications so that we can see if we will be able to support your requirements. The series is available in small SOT-26W and USP-6C.
APPLICATIONS
Clock for controlling a Imaging dot (LCD) DSC (Digital still camera) DVC (Digital video camera) PND (Car navigation system) UMPC (Ultra Mobile Personal Computer) SSD (Solid State Disk) Digital Photo Frame Microcomputer and HDD drives Cordless phones & Wireless communication equipment Various system clocks
FEATURES
Input Frequency Range Output Frequency Range Output Divider (N) Range Input Divider (M) Range Operating Voltage Range Low Power Consumption Small Packages
: 8kHz ~ 36MHz (*1) : 1MHz ~ 100MHz (fQ0=fCLKin x N/M) (*1) : 1 ~ 4095 (*1) : 1 ~ 2047(*1) : 2.50V ~ 5.50V (*1) : 10 A MAX. when stand-by (*2) : SOT-26W, USP-6C
*1: The series are semi-custom products. Specifications for each product are limited within the above range. The input frequency range is set within 5 of customer's designated typical frequency. Please note that setting of your some requirements may not be possible due to the specification limits of this series. *2: When the IC is in stand-by mode, the output becomes high impedance and the IC stops operation.
TYPICAL APPLICATION CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTICS
PLL Output signal jitter 2 (tJ2) (synchronous to an input signal) XC25BS8001xx (610 multiplier, input 15kHz (TYP.))
*1
Input Signal fCLKin
Output jitter tJ2=20(ns)
Output Signal fQ0
*1: CIN (by-pass capacitor, 0.1 F) and LPF should be connected to the IC as close as possible.
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XC25BS8Series
PIN CONFIGURATION
Q0
6
VSS
5
CE
4
VDD
6
1 Q0 2 VSS 3 CE
* The dissipation pad (TAB) of the bottom view of the USP-6C package should be connected to the VSS (No. 2) pin.
LPF 5 CLKin 4
1 2 3
VDD
LPF
CLKin
SOT-26W (TOP VIEW)
USP-6C (BOTTOM VIEW)
PIN ASSIGNEMNT
PIN NUMBER SOT-26W 6 5 4 3 2 1 USP-6C 1 2 3 4 5 6 PIN NAME Q0 VSS CE CLKin LPF VDD FUNCTION Clock Output Ground Stand-by Control (*) Reference Clock Signal Input Device connection for Low Pass Filter Power Input
FUNCTION LIST
CE Q0 'H'' Signal Output 'L'' or OPEN High Impedance
*H: High level input L: Low level input stand-by mode
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XC25BS8
Series
PRODUCT CLASSIFICATION
Ordering Information XC25BS8
DESIGNATOR DESCRIPTION Product Number Packages Device Orientation SYMBOL 001~ M E R L DESCRIPTION : Serial number based on internal standards e.g. product number 001 =001 : SOT-26W : USP-6C : Embossed tape, standard feed : Embossed tape, reverse feed
BLOCK DIAGRAM
VSS
Q0
Output Buffer
CE Rdn
1/N Counter VCO Charge Pump Phase Detector 1/M Counter
VDD
CLK
LPF C1
C1Low Pass Filter Ceramic Capacitor Please set as an external components between LPF Pin and VSS Recommended components (1608 Type) C10.1F ---- Taiyo yuden EMK107BJ104KA
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage CLKin Pin Input Voltage CE Pin Input Voltage Q0 Pin Output Voltage Q0 Pin Output Current Power Dissipation SOT-26W USP-6C SYMBOL VDD VCK VCE VQ0 IQ0 Pd Topr Tstg RATINGS VSS - 0.3 VSS + 7.0 VSS - 0.3 VDD + 0.3 VSS - 0.3 VDD + 0.3 VSS - 0.3 VDD + 0.3 50 250 100 -40 +85 -55 +125 V V V V
Ta=25
UNITS
mA mW mW
Operating Temperature Range Storage Temperature Range
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XC25BS8Series
ELECTRICAL CHARACTERISTICS
Characteristics example by product series
*1: The chart below introduces the products with typical specification characteristics. *2: For other part number with other input-output frequency or multiplication, please ask Torex sales contacts. *3: The series are semi-custom products. Specifications for each product are limited within this catalog range. The input frequency range is set within 5% of customer's designated typical frequency.
XC25BS8001xx610 multiplication) PARAMETER Input Frequency Multiplier Ratio PLL Output Frequency XC25BS8002xx1220 multiplication) PARAMETER Input Frequency Multiplier Ratio PLL Output Frequency XC25BS8003xx256 multiplication) PARAMETER Input Frequency Multiplier Ratio PLL Output Frequency XC25BS8004xx4 multiplication) PARAMETER Input Frequency Multiplier Ratio PLL Output Frequency XC25BS8005xx8 multiplication) PARAMETER Input Frequency Multiplier Ratio PLL Output Frequency SYMBOL fCLKin N/M fQ0 MIN. TYP. 9.000 8 72.000 MAX. UNITS MHz Multiplier MHz SYMBOL fCLKin N/M fQ0 MIN. TYP. 20.000 4 80.000 MAX. UNITS MHz Multiplier MHz SYMBOL fCLKin N/M fQ0 MIN. TYP. 48.000 256 12.288 MAX. UNITS kHz Multiplier MHz SYMBOL fCLKin N/M fQ0 MIN. TYP. 15.000 1220 18.300 MAX. UNITS kHz Multiplier MHz SYMBOL fCLKin N/M fQ0 MIN. TYP. 15.000 610 9.150 MAX. UNITS kHz Multiplier MHz
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XC25BS8
Series
ELECTRICAL CHARACTERISTICS (Continued)
Recommended Operating Conditions: XC25BS8001xx (610 multiplication, Input 15kHz (TYP.)) 5.0V (TYP.)
Tested below Ta=25 C
O
PARAMETER Supply Voltage 5.0V Input Frequency Multiplier Ratio Output Frequency Capacity Overload (*3) Output Start Time
NOTE:
(*2)(*3)
SYMBOL VDD fCLKin N/M fQ0 CL tSTART
CONDITIONS 5.0V (TYP.) operation
(*1)
MIN. 4.50 14.250 610 8.693 0.05
MAX. 5.50 15.750 96.075 15 20
UNITS V kHz MHz pF ms
Typical value is shown (*1)
(*1)
fCLKin14.250kHz
*1: The values are measured when a capacitor CIN=0.1 between LFP and VSS pins.
F is connected between VDD and VSS pins,
a capacitor C1=0.1
F is connected
*2: It is a time to get stable output signal from Q0 pin after the CE pin is turned on while applying supply voltage to the VDD pin and applying the input signal to the CLKin pin. *3: Values indicated are design values which are not guaranteed 100%.
DC Characteristics: XC25BS8001xx (610 multiplication, Input 15kHz (TYP.) ) 5.0V (TYP.)
PARAMETER H Level Input Voltage L Level Input Voltage H Level Input Current L Level Input Current H Level Output Voltage L Level Output Voltage Supply Current 1 Supply Current 2 CE H Level Voltage CE L Level Voltage CE Pull-Down Resistance 1 CE Pull-Down Resistance 2 Output Off Leak Current SYMBOL VIH VIL IiH IiL VOH VOL IDD1 IDD2 VCEH VCEL Rdn1 Rdn2 IOZ CE= VDD CE= 0.1*VDD VDD=5.50VCE= 0.0V VCLKin=VDD-0.5V VCLKin=0.5V VDD=4.50VIOH=-8mA VDD=4.50VIOL= 8mA VDD=5.50VCE= 5.50V VDD=5.50VCE= 0.0V CONDITIONS MIN. 4.00 -5.0 3.60 4.00 0.1 2 TYP. 4.0 0.4 20 MAX. 1.00 5.0 0.65 8.0 20 1.00 0.8 40 10 UNITS V V A A V V mA A V V M k A
Ta=25
CIRCUIT
NOTE: TEST CONDITION: VDD=5.0V, fCLKin=15kHz, C1=0.1
F, Multiplier ratio=610, No load
AC Characteristics: XC25BS8001xx (610 multiplication, Input 15kHz (TYP.)) 5.0V (TYP.)
Ta=25
PARAMETER Output Rise Time Output Fall Time
(*1) (*1)
SYMBOL tR tF Duty tJ1 tJ 1
CONDITIONS (20% ~ 80%) (20% ~ 80%) (Output Period)
MIN. 45 -
TYP. 2.5 2.5 50 40 15.0
MAX. 5.0 5.0 55 -
UNITS ns ns ps ns
CIRCUIT
Output Signal Duty Cycle (*1) PLL Output Signal Jitter 1 (*1) PLL Output Signal Jitter 2
NOTE:
(*1)
Peak to Peak (Output Tracking)
F, Multiplier ratio=610, CL=15pF
TEST CONDITION: VDD=5.0V, fCLKin=15kHz, C1=0.1
*1: Values indicated are design values, which are not guaranteed 100%.
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XC25BS8Series
ELECTRICAL CHARACTERISTICS (Continued)
Recommended Operating Conditions: XC25BS8002xx (1220 multiplication, Input 15kHz (TYP.)) 3.3V (TYP.)
Tested below Ta=25 C
O
PARAMETER Supply Voltage 3.3V Input Frequency Multiplier Ratio Output Frequency Capacity Overload Output Start Time
NOTE:
(*3) (*2)(*3)
SYMBOL VDD fCLKin N/M fQ0 CL tSTART
CONDITIONS 3.3V (TYP.) operation
(*1)
MIN. 2.97 14.250 1220 17.385 0.05
MAX. 3.63 15.750 19.215 15 20
a capacitor C1=0.1
UNITS V kHz MHz pF ms
F is connected
Typical value is shown (*1)
(*1)
fCLKin14.250kHz
*1: The values are measured when a capacitor CIN=0.1 between LFP and VSS pins
F is connected between VDD and VSS pins,
*2: It is a time to get stable output signal from Q0 pin after the CE pin is turned on while applying supply voltage to the VDD pin and applying the input signal to the CLKin pin. *3: Values indicated are design values which are not guaranteed 100%.
DC Characteristics: XC25BS8002xx (1220 multiplication, Input 15kHz (TYP.)) 3.3V (TYP.)
PARAMETER H Level Input Voltage L Level Input Voltage H Level Input Current L Level Input Current H Level Output Voltage L Level Output Voltage Supply Current 1 Supply Current 2 CE H Level Voltage CE L Level Voltage CE Pull-Down Resistance 1 CE Pull-Down Resistance 2 Output Off Leak Current SYMBOL VIH VIL IiH IiL VOH VOL IDD1 IDD2 VCEH VCEL Rdn1 Rdn2 IOZ CE= VDD CE= 0.1*VDD VDD=3.63VCE= 0.0V
F, Multiplier ratio=1220, No load
Ta=25
CONDITIONS
MIN. 2.70 -
TYP. 2.0 0.6 30 -
MAX. 0.60 3.0 0.45 4.0 10 0.45 1.2 60 10
UNITS V V A A V V mA A V V M k A
CIRCUIT
VCLKin=VDD-0.3V VCLKin=0.3V VDD=2.97VIOH=-4mA VDD=2.97VIOL= 4mA VDD=3.63VCE= 3.63V VDD=3.63VCE= 0.0V
-3.0 2.38 2.70 0.1 5 -
NOTE: TEST CONDITION: VDD=3.0V, fCLKin=15kHz, C1=0.1
AC Characteristics: XC25BS8002xx (1220 multiplication, 15kHz(TYP.)) 3.3V (TYP.)
PARAMETER Output Rise Time Output Fall Time
(*1) (*1) (*1)
Ta=25
SYMBOL tR tF Duty tJ1 tJ 1
CONDITIONS (20% ~ 80%) (20% ~ 80%) (Output Period)
MIN. 45 -
TYP. 4.0 4.0 50 20 30.0
MAX. 8.0 8.0 55 -
UNITS ns ns ps ns
CIRCUIT
Output Signal Duty Cycle
PLL Output Signal Jitter 1 (*1) PLL Output Signal Jitter 2 (*1)
NOTE:
Peak to Peak (Output Tracking)
TEST CONDITION: VDD=3.3V, fCLKin=15kHz, C1=0.1 F, Multiplier ratio=1220, CL=15pF *1: Values indicated are design values, which are not guaranteed 100%.
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XC25BS8
Series
NOTE ON USE
(1) Please use this IC within the stated absolute maximum ratings. The IC is liable to malfunction should the ratings be exceeded. (2) The series is an analog IC. Please use a 0.01 F to 0.1 F of a by-pass capacitor. (3) The constant of the LPF element of this IC is preset. Always use the capacitance value (=0.1 F) specified by us for the external ceramic capacitor (C1) for LPF. Operating this IC with a capacitor of the wrong capacitance will cause erroneous operation. (4) Rq0 shown in the Typical Application Circuit is a matching resistor. The use is recommended in order to counter unwanted radiations. (5) Please place the by-pass capacitor and the matching resistor as close to the IC as possible. The IC may not operate normally if the by-pass capacitor is not close enough to the IC. Further, the unwanted radiation may occur between the resistor and the IC pin if the matching resistor is not close enough to the IC. (6)When the CE pin is not controlled by external signals, it is recommended that a time constant circuit of R1=1k = 0.1 F be added for stability. (7) With this IC, output is achieved by dividing and multiplying the reference oscillation by means of the PLL circuit. In cases where this output is further used as a reference oscillation of another PLL circuit, it may be that the final output signal's jitter increases; therefore, all necessary precautions should be taken to avoid this. (8) It is recommended that a low noise power supply, such as a series regulator, be used as the series' supply voltage. Using a power supply such as a switching regulator may enlarge the jitter, which in turn may lead to abnormal operation. Please confirm its operation with the actual device. (9) For operating the IC normally, please take procedures below when applying voltage to the series' input pin: 1) Apply power source while the CE pin is "L" level with no clock input (high-Impedance or "L"), 2) Input the clock, 3) At least 100 s after applying clock input, change the CE pin into "H" level and then to enable. The IC has to be started by inputting the clock once the power rises completely. The CE pin, then, should be enabling. If the CE pin becomes enable and the clock is inputted before the power rises completely, an internal reset circuit does not operate normally which may cause to generate extraneous frequency. C1
eg.)Matching Resistance Rq0 and Device for Time constant circuit (R1,C2are connected, Package: SOT-26W
7/14
XC25BS8Series
NOTE ON USE (Continued)
Instructions on Pattern Layout
1. In order to stabilize VDD voltage level, we recommend that a by-pass capacitor (CIN) be connected as close as possible to
the VDD and VSS pins. 2. Please mount the low pass filter capacitor C1(=0.1 F) as close to the IC as possible. 3. Make the pattern as close to the IC as possible and use thick, short connecting traces to reduce the circuit impedance. 4. Make sure that the VSS (GND) traces are as thick as possible, as variations in ground potential caused by noise may result in instability of this product.
< Reference pattern layout > * We prepare the evaluation board PCB, which is designed by the below layout pattern.
1. SOT-26W Reference Pattern Layout
2. USP-6C Reference Pattern Layout
QO
CL CIN
CE
VDD VSS
C1
CLK
TOREX XC25BS8
8/14
IC
XC25BS8
Series
TEST CIRCUIT
Determination, etc of output frequency and duty Duty
Operating Supply Voltage H Level Input Voltage L Level Input Voltage CE "H" Level Voltage CE "L" Level Voltage Output Rise Time Output Fall Time Output Signal Duty PLL Output Signal Jitter 1 PLL Output Signal Jitter 2
CE
Determination, etc of CE input voltage
H Level Input Current L Level Input Current
H Level Output Voltage L Level Output Voltage
VDD
pulse
Checking output waveform When measuring VOL: turn the switch on to R1 When measuring VOH: turn the switch on to R2
Q0 CE
R2
SW
CLKin VSS LPF
R1
Input CLK in
C1
When measuring VOH Q0 output waveform
When measuring VOL Q0 output waveform
9/14
XC25BS8Series
TEST CIRCUIT (Continued)
Supply Current 1 Supply Current 2
A
pulse Input CLK in
VDD CLKin VSS
Q0
SW="H" IIDD1 DDI SW="H": measurement SW="L" : IDD2 SW="L" measurement IDD2
LPF
CE
SW="L" C1
CE Pull-Down Resistance 1 CE Pull-Down Resistance 2
Measuring IRdn1 Rdn1=VDD / IRdn1 Measuring IRdn2 Rdn2=(0.1 x VDD) / IRdn2
Output Off Leak Current
VDD Q0 A CE VSS
LPF
CLKin
C1
10/14
XC25BS8
Series
AC CHARACTERISTICS TEST WAVEFORM
1) Output Rise Time, Output Fall Time
Output Waveform
DUTY Test Level Q0 Output Signal Waveform
tR
2) Duty Cycle
Output Waveform
tF
Q0 Output Signal
Duty Cycle Measurement Level DUTY
Duty Cycle =(TW / T)
100 %
3) Output Start Time
CE Input Signal Waveform
tSTART
Q0 Output Signal Waveform
11/14
XC25BS8Series
TYPICAL PERFORMANCE CHARACTERISTICS
Synchronous Output Frequency vs. Supply Voltage
XC25BS8001xx (610 multiplication, Input 15kHz(TYP.))
XC25BS8001N/M=610Q0 vs VDD
30 25 Q0MH 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 VDD(V) 5.0 5.5 6.0
25 -40 MIN_Q0 85 MAX_Q0
12/14
XC25BS8
Series
PACKAGE INFORMATION
SOT-26W USP-6C
(unit : mm)
2.90.2 0.4
+0.1 -0.05
6
5
4
00.1 1.80.2 2.80.2
1
(0.95)
2
1.90.2
3
0.15 -0.05
+0.1
1.10.1
1.3MAX
SOT-26W Package
MIN0.1
* No. 1 pin is wider than the other pins. Soldering fillet surface is not formed because the sides of the pins are not plated.
USP-6C Reference Pattern Layout
USP-6C Reference Metal Mask Design
13/14
XC25BS8Series
1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this catalog may be copied or reproduced without the prior permission of TOREX SEMICONDUCTOR LTD.
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